smsc sch5017 product preview revision 0.5 (05-24-07) data brief product features sch5017 super i/o with temperature sensing, quiet auto fan and glue logic ? general features ? 3.3 volt operation (sio block is 5 volt tolerant) ?lpc interface ? programmable wake-up event interface ? pc99, pc2001 compliant ? acpi 2.0 compliant ? multiplexed command, address and data bus ? serial irq interface compatible with serialized irq support for pci systems ? pme interface ? isa plug-and-play compatible register set ? 25 general purpose input/output pins ? system management interrupt ? ac power failure recovery ? watchdog timer ? 2.88mb super i/o floppy disk controller ? licensed cmos 765b floppy disk controller ? software and register compatible with smsc's proprietary 82077aa compatible core ? supports one floppy drive ? configurable open drain/push-pull output drivers ? supports vertical recording format ? 16-byte data fifo ? 100% ibm? compatibility ? detects all overrun and underrun conditions ? sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption ? dma enable logic ? data rate and drive control registers ? 480 address, up to eight irq and three dma options ? support 3 mode fdd ? enhanced digital data separator ? 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates ? programmable precompensation modes ? serial ports ? two full function serial ports ? high speed ns16c550a compatible uarts with send/receive 16-byte fifos ? supports 230k and 460k baud ? programmable baud rate generator ? modem control circuitry ? 480 address and 15 irq options ? infrared port ? multiprotocol infrared interface ? irda 1.0 compliant ? sharp ask ir ? 480 addresses, up to 15 irq ? multi-mode? parallel port with chiprotect? ? standard mode ibm pc/xt?, pc/at?, and ps/2? compatible bi-directional parallel port ? enhanced parallel port (epp) compatible - epp 1.7 and epp 1.9 (ieee 1284 compliant) ? ieee 1284 compliant enhanced capabilities port (ecp) ? chiprotect circuitry for protection ? 960 address, up to 15 irq and three dma options ? keyboard controller ? 8042 software compatible ? 8 bit microcomputer ? 2k bytes of program rom ? 256 bytes of data ram ? four open drain outputs dedicated for keyboard/mouse interface ? asynchronous access to two data registers and one status register ? supports interrupt and polling access ? 8 bit counter timer ? port 92 support ? fast gate a20 and kreset outputs ? motherboard glue logic ? ide reset output ? (4) buffered pci reset outputs with software controlled reset capability - default transparent ? 3vsb gate and 3v gate signal generation ? front panel reset debouncing and power good signal generation ? power supply turn on circuitry with support for power button on ps/2 keyboard ? resume reset signal generation ? smbus isolation circuitry (2 sets external and 1 set internal for hardware monitoring block) ? smbus 2.0 compliant interface for hardware monitoring ? led control (2)
order number: SCH5017-NW for 128-pin, qfp lead-free rohs compliant package 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2007 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relati ng to smsc products are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this information does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporation (?smsc?). produc t names and company names are th e trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation an y and all implied warranties of merchantabil ity, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liabl e for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages. super i/o with temperature sensing, quiet auto fan and glue logic revision 0.5 (05-24-07) 2 smsc sch5017 product preview ? fan control ? 5 pwm (pulse width modulation) outputs ? two and three piece linear fan function options. ? low frequency and high frequency pwm support ? 6 fan tachometer inputs ? programmable automatic fan control based on temperature ? interrupt pin for out-of-limit fantach events ? fantach events generate pme?s and/or speaker warning ? temperature monitor ? monitoring of two remote thermal diodes ? internal ambient temperature measurement ? limit comparison of all monitored values ? interrupt pin for out-of-limit temperature indication ? thermal events generate pme?s and/or speaker warning ? configurable offset for inter nal or external temperature channels. ? voltage monitor ? monitor power supplies (5v, +5vtr, +12v, vccp, vbat, vtr, and vcc) ? limit comparison of all monitored values ? interrupt pin for out-of-limit voltage indication ? voltage events generate pme?s and/or speaker warning ? security features ? security key register (32 byte) for device authentication ? 6 vid (voltage identification) inputs ? phoenix keyboard bios rom ? 128-pin, qfp lead-free rohs compliant package
super i/o with temperature sensi ng, quiet auto fan and glue logic smsc sch5017 3 revision 0.5 (05-24-07) product preview general description the sch5017 is a 3.3v (super i/o block is 5v tolerant) pc99/pc2001 compliant super i/o controller with an lpc interface. sch5017 also includes ha rdware monitoring capabilities, enhanced security features, power control logic and motherboard glue logic. the sch5017's hardware monitoring capability includes temperature, voltage and fan speed monitoring. it has the ability to alert the system to out-of-limit conditions and automatically control the speeds of multiple fans. there are four analog input s for monitoring external voltages of +5v, +5vtr, +12v and vccp (core processor voltage), as well as internal monitoring of the sio's vcc, vtr, and vbat power supplies. the sch5017 includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for me asuring ambient temperat ure. the nhwm_int pin is implemented to indicate out-of-limit temperat ure, voltage, and fantach conditions. the hardware monitoring block of the sch5017 is accessible vi a the system management bus (smbus). the same interrupt event reported on the nhwm_int pin al so creates pme wakeup events and speaker alarm annunciation. the sch5017 also allows for a two or three piece linear fan function. the motherboard glue logic includes va rious power management and system logic including generation of nrsmrst, smbus buffers, and buffered pci reset outputs. the sch5017 incorporates complete legacy super i/o functionality including an 8042 based keyboard and mouse controller, an ieee 1284, epp, and ecp compatible paralle l port, one serial port that is 16c550a uart compatible, one irda 1.0 infrared por ts, and a floppy disk controller with smsc's true cmos 765b core and enhanced digital data separator, the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/at architecture s and is software and register compatible with smsc's proprietary 82077aa core. system related func tionality, which offers flexibility to the system designer, general purpose i/o control functions, control of two led's, and fan control using fan tachometer inputs and pulse width modulator (pwm) outputs the sch5017 is acpi 1.0/2.0 compatible and ther efore supports multiple low power-down modes. it incorporates sophisticated power control circuitr y (pcc), which includes support for keyboard and mouse wake-up events. the sch5017 supports the isa plug- and-play standard register set (v ersion 1.0a). the i/o address, dma channel and hardware irq of each logical device in the sch5017 may be reprogrammed through the internal configuration registers. ther e are up to 480 (960 - parallel port) i/o address location options, a serialized irq interface, and three dma channels.
super i/o with temperature sensing, quiet auto fan and glue logic revision 0.5 (05-24-07) 4 smsc sch5017 product preview block diagram figure 1 sch5017 block diagram leds led2* led1* internal bus (data, address, and control lines) power mgmt io_pme_s5* io_smi* gp1[0:4]*, gp21*,gp22* gp27*, gp32*,gp33* gp36*, gp37* , gp4[0,2,3]* gp5[0:1]*, gp6[0:1]* note 1: this diagram does not show power and ground connections. note 2: signal names followed by an asterisk (*) are located on multifunction pins. this diagram is designed to show the various functions available on the chip and should not be used as a pin layout. clock gen clk32 clocki wdt 32 byte security key register ndsr1, ndtr1 ndcd1, nri1 power control and recovery ` slp_s3#, slp_s5# pwrgd_cpu , pwrgd_3v n3vsb_gat e n3v_gate nrsmrst nfprst, pb_in# pwrgd_ps nhwm_int vid0 vid1 vid2 vid3 vid4 vid5 / fantach3 +5v_in +5vtr_in vccp_in +12v_in remote1- remote1+ remote2- remote2+ pwm1/xtest out pwm2 pwm3/ addr_en# fantach1 fantach2 fantach4/ addr_sel pwma*, pwmb* fantacha* fantachb* s m b u s sda sclk hardware monitor general purpose i/o io_pme_s3* vcc vtr vbat slp_s3# slp_s5# hwn_int 14.318mhz 96 mhz pci_reset# wdt* ser_irq lad[3:0] lframe# ldrq# pci_reset# pci_clk lpc bus interface serial irq smbus isola- tion switch sda1 sclk1 sda2 sclk2 smsc proprietary 82077 compatible floppydisk controller with digital data separator & write precom- pensation nrdata, nwdata ndir, nstep nmtr0, ntrk0, inndex drvden0*, nwrtprt nwgate, nhdsel ndskchg, nds0, high-speed 16550a uart port 1 txd1*, rxd1 ncts1, nrts1* multi-mode parallel port with chiprotect tm / fdc mux (see lpc47b27x) pd[7,0] busy, slct, pe, nerror, nack nstrobe, ninit, nslctin, nalf intruder detection nintrd_in keyboard/mouse 8042 controller kclk*, kdat* mclk*, mdat* a20m* nkbdrst* pci reset outputs npcirst_out[1:4]* nide_rstdrv* speaker speaker high-speed 16550a uart port 2 txd2 (irtx)*, rxd2 (irrx)* dsr2*, dtr2* dcd2*, ri2* cts2*, rts2 *
super i/o with temperature sensi ng, quiet auto fan and glue logic smsc sch5017 5 revision 0.5 (05-24-07) product preview package outline figure 2 128-pin qfp package outline, 14x20x2.7 body, 3.2 mm footprint. notes: 1. controlling unit: millimeter. 2. controlling unit: millimeter. 3. tolerance on the position of the leads is 0.04 mm maximum. 4. package body dimensions d1 and e1 do not include the mold protrusion. 5. maximum mold protrusion is 0.25 mm. 6. dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane. 7. details of pin 1 identifier are optional but must be located within the zone indicated. table 1 128-pin qfp package parameters min nominal max remarks a ~ ~ 3.4 overall package height a1 0.05 ~ 0.5 standoff a2 2.55 ~ 3.05 body thickness d 23.00 23.20 23.40 x span d1 19.90 20.00 20.10 x body size e 17.00 17.20 17.40 y span e1 13.90 14.00 14.10 y body size h 0.09 ~ 0.20 lead frame thickness l 0.73 0.88 1.03 lead foot length l1 ~ 1.60 ~ lead length e 0.50 basic lead pitch q0 o ~7 o lead foot angle w 0.10 ~ 0.30 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.30 lead foot radius ccc ~ ~ 0.08 coplanarity
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